This invention relates to regenerators, data recovery, and data separator systems for information storage mediums such as magnetic floppy disk devices and more particularly to phase correction techniques for normalizing read data bits at a prescribed position in a detection window of a window signal.
FIG. 1 is a prior art regeneration system 10 for a floppy disk drive and comprises a floppy disk 12, a read/write head 14, a preamplifier 16, a one-shot multivibrator 18, and a phase locked loop (PLL) 20 having a phase comparator 22, a low-pass filter 24, and a voltage controlled oscillator (VCO) 26. System 10 is alternatively called a data recovery or data separator system by those skilled in the art. Phase comparator 22 employs a charge pump (not shown). An oscillating signal "T.sub.1 " is output by VCO 26 and input to a data normalizer 28. A read data (RD) signal (having a frequency "f.sub.1 ") output by one-shot circuit 18 is also connected to normalizer 28. A signal "T.sub.2 " (oscillating at a frequency "f.sub.2 ") is also generated at one half of the frequency of signal "T.sub.1 " by using a divider in data normalizer 28. A discriminator 30 extracts a signal "X" from a window signal "W" and a signal "Z". System 10 uses, for example, a modified frequency modulation (MFM) encoding scheme on floppy disk 12. One-shot multivibrator 18 functions to shape a waveform "P" from preamplifier 16 into signal "RD". Phase comparator 22 compares the phase of signal "RD" to synchronizing signal "T.sub.2 " and generates a phase error signal "E". Low-pass filter 24 functions as a loop filter, and produces a DC correction voltage "C" having a magnitude that is proportional to the phase error between "f.sub.1 " and "f.sub.2 " at comparator 22. VCO 26 varies the frequency of signal "T.sub.1 " up or down appropriately, depending on voltage "C".
System 10 works in the following way. If the frequency "f.sub.1 " of signal "RD" goes higher than average, due, for example, to low-frequency wow and flutter of floppy disk 12, a phase difference develops between frequencies "f.sub.1 " and "f.sub.2 ". This causes a phase error signal "E" to be generated at the output of phase comparator 22. Low-pass filter 24 then filters and outputs this as correction voltage "C". Since VCO 26 is a voltage controlled oscillator, its output frequency is controlled by changes in voltage "C". The oscillation frequency "T.sub.1 ", in this case, moves closer to two times "f.sub.1 ", such that "f.sub.1 " approaches "f.sub.2 " (because "T.sub.1 " is divided by two). When "f.sub.1 " equals "f.sub.2 ", comparator 22 produces a voltage that causes VCO 26 to oscillate at twice "f.sub.2 ". equilibrium voltage will not necessarily be zero volts, and instead, will be dependent on the exact circuit design of VCO 26. The net result of the above is that a synchronizing signal (here "T.sub.2 ") is obtained which will track wow and flutter induced fluctuations in signal RD.
FIG. 2 illustrates that data normalizer 28 typically comprises a divide-by-two divider 32, a pair of D-type flip-flops 34 and 36, a two-input OR-gate 38, and a one shot multivibrator 40. The output of VCO 26 (signal "T.sub.1 ") is connected to the clock input C.sub.1 of divider 32 and is divided by a factor of two at outputs Q.sub.1 and Q.sub.1. A window signal "W", coming from master output M of divider 32, has a phase that is delayed one-half .pi. (90.degree.) with respect to output Q.sub.1. A flip-flop 34 receives signal "RD" at its clock input C.sub.2 and has the inverted output Q.sub.1 of the divide-by-two divider 32 applied to both its data input D.sub.2 and reset input R.sub.2. The data input of a flip-flop 36 receives signal "RD" at its clock input C.sub.3 and has the output Q.sub.1 of divider 32 connected to both data input D.sub.3 and reset input R.sub.3. OR-gate 38 has two inputs, one of which is connected to output Q.sub.2 of flip-flop 34 and the other of which is connected to output Q.sub.3 of flip-flop 36. A negative edge-sensitive one-shot multivibrator 40 senses the falling edge of synchronizing signal "T.sub.2 " at the output of OR-gate 38, and generates a signal "Z" (comprising a stream of narrow pulses).
FIG. 3 shows the timing relationships among the various signals in system 10 and especially those in data normalizer 28. Flip-flop 36 demodulates signal "RD" and functions as an MFM decoder which separates out the desired data bit sequence. Flip-flop 34 functions to extract the so-called MFM clock bit. Output Q.sub.3 corresponds to the data pulse sequence, and output Q.sub.2 corresponds to the clock pulse and indicates the bit interval. Signal "RD" has a pulse width one-quarter of the fundamental period and is synchronized with signal "T.sub.1 ". Output Q.sub.3 of flip-flop 36 goes high if signal "RD" goes high while output Q.sub.1 of divider 32 is high. Output Q.sub.3 goes low immediately when output Q.sub.1 goes low. Output Q.sub.2 of flip-flop 34 goes high if signal "RD" goes high while the inverted output Q.sub.1 of divider 32 is high. Output Q.sub.2 goes low immediately when output Q.sub.1 goes low. The outputs Q.sub.3 and Q.sub.2 are combined in OR-gate 38 and are synchronized with signal "RD" to generate synchronizing signal "T.sub.2 " having the same phase. Synchronizing signal "T.sub.2 " is input to multivibrator 40 and produces the narrow pulse width code sequence "Z". Each data pulse rise in signal "Z" is triggered by a falling edge of synchronizing signal "T.sub.2 " (and is not generated by the falling edge of signal "RD"). Since window signal "W" is the master output M of divider 32, the data pulse of code sequence "Z" appears at the center of a detection window width "w". In this way, the read data is normalized with respect to the window signal "W". The MFM code sequence (1101 . . . ), shown in FIG. 3, has the clock bit removed in a later stage and results in a demodulated code sequence (110 . . . ). Since data pulses in code sequence "Z" are produced from the edges of the output Q.sub.1 and inverted output Q.sub.1, the phases of signal "RD" and synchronizing signal "T.sub.2 " are synchronized and the data pulse of code sequence Z is always generated at the center of detection window width "w" even while experiencing wow and flutter fluctuations (low-frequency fluctuations below one kilohertz). Normalizing the data pulse to be at the center of detection window width "w" is important since window signal W and code sequence Z can have different amounts of delay due to differences in cable wiring to discriminator 30. A sufficient phase margin in the data pulse must be designed-in to prevent it from deviating outside detection window width "w" as much as possible.
FIG. 4 shows the timing of each of the signals in data normalizer 28 when a large peak shift occurs in the signal "RD". PLL 20 is designed to follow wow and flutter fluctuations and other low-frequency fluctuations, and it generates synchronizing signals "T.sub.1 " or "T.sub.2 " by following frequency fluctuations in signal "RD". It also follows phase shifts (peak shifts) in the read data pulse that are randomly generated by magnetic interference between adjacent bits on the magnetic disk. When a peak shift occurs, such as that indicated by the hatched areas in signal "RD" in FIG. 4, a pulse rise occurs and output Q.sub.1 is high, rather than output Q.sub.1 being high. The pulse which should occur in output Q.sub.3 (as indicated by a dashed line in FIG. 4) is not generated, and, instead, a pulse in output Q.sub.2 as indicated by the dashed line in FIG. 4, is generated. This results in the appearance of a pulse (hatched area) in code sequence Z in FIG. 4 which causes the bit to shift. Since this pulse with a shifted bit does not exist in detection window width "w" of the window signal, a recording code sequence for example of "110 . . . " will be incorrectly read as "100 . . . ". When a pulse with a large bit shift occurs, the oscillation frequency of VCO 26 will fluctuate, and synchronizing signal "T.sub.1 " ("T.sub.2 ") which follows this phase delay is generated. This fluctuation of the synchronizing signal, with respect to the delayed peak shift, reduces the phase margin of the next read data pulse and causes it to shift more easily out of the detection window which causes read errors. An excessively large peak shift, as shown in FIG. 4, can easily occur due to a problem in the drive circuit, etc. However, when small peak shifts occur that are not large enough to cause a read error, PLL 20 tries to follow it, but if a peak shift in the opposite direction happens, a read error will probably result. In prior art circuit configurations, read errors result in the occurrence of peak shifts in rapid succession.
Phase shifts of 20.degree. to 30.degree. are normal in operation, and perfect synchronization is essentially impossible. Peak shifts occur randomly and usually comprise both low-frequency and high-frequency components. Since PLL 20 is designed to follow low-frequency wow and flutter (below approximately one kilohertz), it essentially follows peak shifts that have relatively low-frequency components. The advance and delay margins are generally not balanced, so a read error can occur due to mutual differences in the amounts of delay of the two margins in the discriminator. During normal operation, VCO 26 also has a jitter component due to the effects of power source fluctuations, so it is easy for read errors to occur, due to the reduced phase margin of peak shifts. In the prior art, it was necessary to carefully design the loop filter or devise such counter-measures as power source stabilization and noise reduction (cable wiring, parts layout on circuit substrate, etc.) to suppress power source fluctuations.
A phase correction circuit placed in a stage before the data normalizer will correct the phases of the read data signal and the oscillation output with respect to each other. The amount by which the phase is adjusted by the phase correction circuit is controlled by the voltage of the loop filter used in the phase synchronizing circuit. A more specific means for solving one of the above problems is to configure the phase correction circuit with a data phase shifting element for setting the VCO to a pull-in range that will follow only low-frequency fluctuations and for uniformly shifting the phase of the read data signal by only a prescribed amount, using a voltage-controlled delay element for variably adjusting the amount of delay of the oscillation output pulse of VCO according to the output voltage of the loop filter. The phase correction circuit can be configured with a voltage-controlled data phase shifting circuit for variably adjusting the amount of pulse phase shift of the read data signal according to the output voltage of the loop filter. A more specific means for solving the above problems simultaneously is to configure the loop filter with a first-stage low-pass filter having a first cut-off frequency and a second-stage low-pass filter having a second cut-off frequency lower than the first cut-off frequency, and to configure the phase correction element with a voltage-controlled data phase shifting circuit which variably adjusts the amount of shift of the pulse phase of the read data signal according to the output voltage of the second-stage low-pass filter, and with a voltage-controlled delay element that adjusts the amount of delay of the oscillation output pulse of the VCO according to the output voltage of the first-stage low-pass filter.
When the voltage controlled oscillator is set to a pull-in range that follows only low-frequency fluctuations, a phase-synchronizing element will not follow fluctuations containing high frequency components such as peak shifts and it mainly follows wow and flutter fluctuations. The occurrence of peak shifts varies the output voltage of the loop filter. Due to this voltage fluctuation, the voltage-controlled delay element adjusts the amount of delay of the oscillation output pulse coming from the voltage-controlled oscillator. That is, the amount of delay of the oscillation output pulse is controlled according to the phase of the peak shift. The phase of the read data signal, however, is uniformly shifted 90.degree., for example, by the data phase shifting element. This is because the pulse which delayed the oscillation output pulse and the pulse of the read data signal are combined. Using this combined signal processing, the data bit pulse in which a peak shift has occurred can be matched without deviation within the detection window width of the window signal in the data normalizer, whereby read errors due to peak shifts are reduced compared to prior art signal processing devices.
The problem of unbalanced phase margins in wow and flutter fluctuations not containing a high-frequency component such as peak shifts is improved by adjusting the phase of the read data signal pulse. By employing a voltage-controlled data phase shifting element as the phase correcting circuit which variably adjusts the amount of shift in the phase of the read data signal pulse according to the output voltage of the loop filter. A fine adjustment in the amount of phase shift is made in response to relatively small phase fluctuations, according to the amount of phase fluctuation, rather than large phase adjustments, such as for peak shifts. Therefore, it is possible to make the advance margin and delay margin of the data bit equal with respect to the window width. Differences between the data bit sequence and the delay of the window signal inevitably occur between the data normalizer and the discriminator in a later stage, but by making the advance margin and the delay margin equal in the data normalizer, the probability of discrimination errors (read errors) occurring is reduced.
An object of the present invention is to offer a highly reliabler regenerator for information recording mediums that will not easily produce read errors when relatively large phase shifts (having high-frequency fluctuations) occur in a read data signal. Another object is to offer a highly reliable regenerator for information recording mediums that makes it difficult for read errors to occur by continually balancing phase margins even when relatively low-frequency fluctuations occur due to wow and flutter fluctuations or power source fluctuations.